Hardware Acceleration of FIR Filter Implementation on ZYNQ SoC

Abstract

Finite impulse response (FIR) filters are widely used in electronic design applications such as digital signal processing, image processing and digital communications. The demand for high performance is increasing particularly in modern real-time signal processing applications. Due to the trade-offs between the performance requirements and design constraints, it is required to develop new design approaches that not only improve the computational efficiency, but also support processors with application-specific hardware accelerators. In this study, design of a low-pass FIR filter operating at 10 MSps sampling rate with 2Mhz cutoff frequency and -40dB/decade attenuation rate is considered as a sample problem, and its performance and cost have been comparatively examined on various hardware platforms. We tested the performance of the designed filter by implementing it on a plain ARM-based processor, FPGA+ARM based System-on-Chip, and an Intel i7-based processor. As a result of the study, we observed that while the filter design implemented on the FPGA+ARM-based SoC works 8.86 times faster than the implemented on a solo ARM-based processor, 1.98 times slower than the implementation on the Intel i7-based processor. In addition, we have determined that the FIR filter design implemented on the FPGA+ARM based SoC exhibits the highest efficiency from the price/performance perspective.