Thermal Design and Performance Evaluation of Gan Power Stage in a 4-Level Totem-Pole PFC

Abstract

Low voltage Gallium Nitride (GaN) power devices are enabling the development of single-phase multi-level power factor correction (PFC) converters for high power density designs due to their superior figure-of-merit. However, despite their lower power losses compared to Si MOSFETs, it is still challenging to remove a few watts of power loss from small packages, which presents a barrier for using GaN in high power converters. To address this issue, this study establishes a 3-D thermal model for chip-scale package GaN devices, and analyses various heat sinking methods for a power stage of a single-phase 4-level PFC structure using the finite element method. The thermal performances of GaN devices with different layouts, board types, and thermal via patterns have been analyzed and verified experimentally on a power stage of a 4-level GaN PFC rated for 3.7 kW, where each of the six GaN devices dissipates 2.3 W.